(1) Field of the Invention
The present invention relates to the formation of integrated circuit devices on semiconductor substrates, and more particularly a structure and a method of fabricating a field effect transistor having self-aligned polysilicon source/drain contacts.
(2) Description of the Prior Art
Today's Ultra Large Scale Integration (ULSI) on the semiconductor substrate is in part due to advances in high resolution photolithographic techniques and to advances in plasma etching of the various conducting and insulating layers on the substrate. In order to construct field effect transistors (FETs) on a chip with high density and improved performance it is necessary to form FETs with submicrometer channel lengths and having reduced source/drain contact areas. However, as this down scaling in device size on the semiconductor substrate surface continues it becomes necessary to also reduce the vertical dimensions, such as making more shallow source/drain diffusions on the FET.
Although the down scaling improves circuit density and performance, a number of adverse effects also occur. For example, when the electrically conducting channel is induced in the space charge region under the gate oxide, by applying a voltage to the gate electrode on the field effect transistor (FET), short channel effects occur when the channel length is scaled down in size. One such effect is the threshold voltage lowering. When the channel length is further reduced and is comparable in length to the source/drain diffusion depth, a considerable amount of the space charge is linked to the source/drain junction depletion region. This results in less charge in the space-charge region being coupled or linked to the gate and the threshold voltage of the FET decreases with decreasing channel length. This threshold voltage dependence on device geometry is undesirable because it makes it difficult to control the electrical design parameters in a manufacturing process.
Other major transistor phenomena that are affected by down scaling and degrade the transistor behavior include channel-length modulation, velocity saturation, mobility degradation, source/drain resistance, punchthrough, drain induced barrier lowering and the likes.
To minimize the short channel effects, it is common practice in the semiconductor industry to fabricate FET structures with Lightly Doped Drains (LDD). These LDD FET structures are fabricated by forming a shallow lightly doped source/drain adjacent to the gate electrode and using a sidewall insulating spacer on the sidewall of the gate electrode to mask the LDD region from further doping. The source/drain contact is then formed by heavily doping the region adjacent to the sidewall spacers to form the ohmic source/drain contacts. Because the LDD region also increases the series resistance and thereby degrades the device performance, it is important to make the contact portion of the source/drain region as low as possible in resistance. Also, because of the down scaling of the FET device size to submicrometer dimensions, to achieve ULSI densities, it becomes even more difficult to align contact openings in the overlying insulating layer to the source/drain contact area.
The common approach to fabricating these LDD FETs in the industry is to dope the heavy doped source/drain contact areas by ion implantation while using the sidewall spacer to mask the LDD region from the heavy doped implant. A silicide layer is usually then formed on the contact to further reduce the resistance. However, the high energy implant in the contact areas lead to crystal damage that is very difficult to anneal out and can generally leads to high leakage currents at the diffused junction. Also, aligning the contacts openings to source/drain areas through the overlying insulator is difficult because of their small area size.
Another serious problem occurs when metal contacts are made to the heavily doped source/drain contact areas. To minimize short channel effects during down scaling, the source/drain contacts in the crystalline substrate are made as shallow as possible. When metal contact, such as aluminum, are made to the substrate the metal is known to react with the silicon. Silicon atoms diffuse from the substrate into the aluminum metal and metal spikes form in the underlying substrate shorting the contact to the substrate. This is particularly so at the source/drain contact edge near the field oxide.
Therefore, there is still a strong need in the semiconductor industry for better methods of forming low resistance source/drain area contacts while retaining the advantages of down scaling and the lightly doped drain on the FET device.